Dual encoder for pcm



Jan. 15, 1963 c. G. DAvls DUAL ENcoDERiFoR PCM Filed July 2, 1959 bmSQQQ v DA V/S /Q E Lb ATTORNEY /NVENTOR 2 Sheets-Sheet 1 QQ @Q Jan. 15,1963 Filed July 2, 1959 C. G. DAVIS DUAL ENCODER FOR PCM T/ME SLOTS` 2 34 5 6 2 Sheets-Sheet 2 D7 l D8 I F IRS T SECOND T H/RD FOURTH SAMPLESAMPLE SAMPL E SAMPL E F/G. 3

(a) ODD /NPU T (L) EVE/v /N PU T 2 OUTPUT (C) PRODUCED BY ODD CHANNEL/NPUT EVEN CHANNEL INPUT (e) rorAL HHH HHH HHHH OUTPUT @Y K. 62MLATTORNEY ruta July 2, tsss, ser. No. assisi s Claims. (ci. 17e-rs) Thisinvention relates to transmitters for pulse type communication systemsand more particularly to encoders for use in the transmitters ofcommunication systems employing pulse code modulation.

In pulse code modulation communication systems, a speech wave or othersignal to be transmitted is sampled periodically to ascertain itsinstantaneous amplitude. The

measuredvinstantaneous amplitudes (PAM signals) are then expressed inpulse codes by encoders. The proper functioning of an encoder isdependent upon both the PAM sample voltage remaining constant during theperiod of encoding and disappearing before the next sarnple appears. Theformer requires good low frequency response; the latter good highfrequency response. This results in wide bandwidth requirements for thesampling gates and to avoid these wide bandwidth requirements earlierPCM systems used two buses and a transfer gate preceding the encoder.The PAM samples were alternately applied to each bus and the transfergate connected the encoder to the proper bus. This approach allowed timeIfor the discharge of one bus while a sample on the other was beingencoded, and vice versa, thus reducing the bandwidth requirements forthe sampling gates.

Because the transfer gate switched between analog signals the problemsof crosstalk and the successful introduction of a D.-C. bias (to produceunipolar pulses from the analog signals) at the transfer gate werepresent. If the nth sample and the (n+l)th sample differed greatly inmagnitude stray capacitance in the transfer -gate would producecrosstalk. Elimination of this crosstalk in the above-described systemwould require expensive and cornplicated transfer gates and drivecircuitry. Transfer gates adequate to perform the switching functionwithout introducing crosstalk may even be equal in cost to a completeencoder.

One object of the invention is to avoid crosstalk in a dual-input PCMencoder in as simple and inexpensive a manner as possible.

A related object is to reduce the bandwidth requirements of the samplingapparatus of a PCM encoder without introducing undesirable interchannelcrosstalk.

Still another object of the invention is to avoid any necessity forhighly complex and expensive gate circuits in a multichannel PCMencoder.

This invention employs dual encoding apparatus which encodes both theodd and even PAM channels separately. Gating means is employed at theoutput of this dual encoding apparatus to transmit each encoded signalto 'la single output channel in the proper time sequence.

Since such gating means is switching between digital signals (which areof equal amplitude), the problem of crosstalk is greatly reduced orcompletely eliminated. A

vcommon control circuit controls the sequential operation atent FIG. 3shows the outputs of the Odd and Even input 70 channels and the totaloutput in response to input samples.

Tice

A seven-digit dual encoder embodying the invention is shown in FIG. 1.The pulse amplitude modulated (PAM) samples to be encoded arealternately applied by means of multiplexing gates to the odd ll andeven 2 input channels ofthe encoder. Control pulses Dl. through DS,shown in FIG. 2, which appear in the first through eighth time slots,respectively, are applied to inputs 3 through l0, respectively, of thecontrol circuit of the encoder'. AND gates 18 through 23 and OR gates24- through 29 comprise the control circuit which sequentially operatesthe encoder. AND circuits and OR circuits have two or more inputs and asingle output. The AND circuit has an output signal only when inputsignals are applied simultaneously to all inputs; the 0R circuit has anoutput if an input signal is applied to any one or more of the inputs.

Flip-fiop circuits 11 through 17 and weighting resistances 30 through 36and Sil through 36 comprise the coding circuit of the encoder. inputs 3through 9 are connected to flip-flops Il through 17, respectively, insuch a manner that the application of a pulse on an input Iline triggersthe respective hip-flop into the one of its two stable conditions, whichcauses a reference voltage to be applied to the weighting resistorsconnected to the output of the ilip-iiop. This operation is calledsetting the flip-flop, and is indicated in the drawing of a flip-flop bythe input line entering the S portion of the box representing theflip-flop with the weighting resistors being drawn to the l portion ofthe box representing the ilipflop. Inputs 4ithrough 9 are connected toone input of AND gates 1S through 23, respectively. The second input toeach AND gate i8 through 23, respectively, is connected to PCM returnline 38. The output of each AND gate 18 through 23, respectively, isconnected to one input of OR gates 24 through 29, respectively. Thesecond input of OR gates 24 through Z9, respectively, is connected toinput line iti. Input line it) is directly connected to flip-flop 17 insuch a manner that the application of a pulse to input line lt) triggersflip-dop 17 into the one of its two stable conditions, which causes aground to be applied to weighting resistors 35 and 36 connected to theoutput of flip-flop i7. This operation is called resetting the Hip-flopand is indicated in the drawing of a iiip-iiop by having the linethrough which the resetting pulse is applied enter the R portion of thebox representing the ilip-ilop and having no output line enter the Oportion of the box representing the iiipflop. The output of OR gates 24through 29, respectively, is connected to flip-flops 1l. through 17,respectively, in such a manner that the appearance of a pulse on theoutput of an OR gate resets the flip-flop.

The outputs of hip-flops il through 37, respectively, are connected toweighting resistors Si) through 3a, respectively, and 3e through 3e',respectively. Odd input channel i is connected by means of conductor t?to the other ends of weighting resistors 3@ through 3a and even inputchannel 2 is connected by means or conductor 43 to the other ends ofresistors 3% through 3.a. Odd input channel i is also connected by meansof conductor d; to the input of error amplifier 39 whose output isconnected to AND gate 4Q. Even input channel 2 is connected by means ofconductor to the input of error amplifier dit whose output is connectedto one input of AND gate Error amplifiers 39 and ai are stable high gainD.C. an-- pliers; each has a low impedance input which acts a currentsumming node in a manner to be described. e second input of AND gate d@is connected to one output of binary cell d3, which is a bistablecircuit with two outputs and a singie input connected to input line iii.The second output of binary cell i3 is connected to the second input ofAND gate 42. The outputs of binary cell d3 are also connected to thecontrol circuits of the odd and even multiplexing gates so that AND gatetti is actuated at the same time that a sample is applied to odd inputchannel ll and AND gate el?. is actuated when a sample is applied toeven input channel i2.. rl`he outputs of AND gates and l2 are connectedto the input of OR gate ist whose output is connected to the input of atriggered blocking oscillator 45. The output of blocking oscillator isconnected to `PCM return line Tad and to the output terminal lo of thedual encoder. Since this dual encoder uses the binary code, weightingresistors Sti through 3o and 3G through 36 are related in binary fashionso that if resistors fr@ and 3i are equal to R, then resistors 3l andSi. are equal to 2R.; resistors 32 and 32 are equal to 4R; resistors 33and 35 are equal to SR; resistors 34 and 3ft are equal to lR; resistors35 and 35' are equal to SZR; and resistors 36 and 36 are equal to 64R.

The PAM samples are alternately applied to the odd 1 and even 2 inputchannels in accordance with the output of binary cell i3 which controlsthe multiplexing gates. During the encoding of a sample the previouslyencoded sample on the other channel is removed and a new sample applied.rl`he exact timing of the removal of the already encoded sample and theapplication of a new sample is unimportant so long as the sample ispresent during the entire coding period. During the eighth time slot thecoder is reset. and the circuits prepared to encode the sample on theother bus. For the sake ot description it is assumed that a PAM signalhas been applied to the odd l channel at the beginning of the first timeslot. Digit control signal Di sets ilipilop lll so that resistor Sti isconnected to a reference voltage. Resistor 3d draws sixty-four units ofcurrent. If the input sample exceeds sixty-four units then current flowsthrough conductor l? to error amplifier 59. Error amplier 39 generatesno output when current flows into it. lf the input sample is less thansixty-four units of current then current flows from error amplier 39 toresistor Eli. When current ilows from error amplifier 39 to resistor 3*@error amplifier 39 produces an output. This output passes throughpreviously actuated AND gate di) and OR gate i4 to the input of blockingoscillator e5. Blocking oscillator l5 generates a pulse output which isreturned to flip- 'ilop ll by means of PCM return line 38, AND gate land OB; gate 24. The pulse output appears at AND gate 1S at the sametime 4as control pulse D2 and therefore passes through AND gate 1S. Thepulse output of a blocking oscillator resets iiip-llop llll to its zeroposition where the output of the ilip-ilop is at ground potential. ifthe PAM sample exceeds sixty-tour units, flip-hop il remains in its setposition but if the PAM sample is less Y than sixty-four units,ilip-tlop "li is reset to its zero posh tion.

During the second time slot, pulse D2 sets flip-flop lll so thatweighting resistor 3i is connected to a reference voltage. Resistor 3ldraws thirty-two units of current. if ilip-op lll is still in its setposition the pulse sample must be greater than 64-l-32 units in orderfor current to flow into the error ampliiier 3%. if the sample is lessthan 64+32 units, current flows from error amplier 39 into resistorliZ.if current flows into error amplii'ier 39 no output is generated andflip-nop l2 remains in its set position. if, however, current flows outof error amplilier 39 there is an output from the error amplifier. Thisoutput passes through AND gate lll and OR gate 4d causing blockingoscillator to generate a pulse which is returned to flip-liep l2 throughPCM return line 3S, AND gate ligand ORgate 25. AND gate 19 passes thispulse since it appears atV AND gate i9 simultaneously with D3. The pulsecauses llip-flop l2 to be reset so that resistor 5l is connected toground. lf nip-flop ll was reset during the first time slot the pulsesample `must be greater than thirty-two units in order for current toflow in the .error amplifier. if 'the sample is less than thirty-two 4units current tlows from error amplifier 39. lf current flows into erroramplifier 39 no output is generated and ilip-flop 12 remains set. if,however, current flows out of error amplifier 39 then there is an outputfrom the error amplifier which causes flip-flop 12 to be reset.

The above-described process continues with each flip-ilop i3 through 17being initially set by the occurrence oi digit pulses D3 through D7. Anoutput pulse is produced as is above described only when it is necessaryfor error amplifier 39 to supply current to the weighting resistorswhose flip-iiops are set. No output pulse is produced when the PAMsample causes current to iiow into error amplier 39. At the end of theseventh time slot, pulse D8 which is applied to input 10 causes binarycell 43 to change states. Since the sampling counters are controlled bythe output of binary cell 43 the next PAM sample is applied to eveninput channel 2. AND gate 42 is actuated by the output of binary cell 43in order to provide a path from error amplifier 41 to OR gate 44. ANDgates 40 and 42 together with OR gate 44 function as a transfer gate.Since input 10 is applied to flip-flops 1l through 115 by means of ORgates 24 through 29, respectively, and is also directly Vconnected toreset fipilop 17, control pulse lD8 resets all `dip-flops 11 through 17in preparation for encoding the next input sample.

,The encoding of the second input sample is Iaccomplished in the samemanner as described for the first input sample except for the fact thatweighting resistors Sil through 36 and error amplifier el are nowconnected to OR gate 445 as AND gate 42 has been actuated by binary cell43. AND gate itl Vis now inoperative. Any sample remaining on odd inputchannel 1 has no eliect on the encoder since the associated circuitry ofodd input channel l has been rendered inoperative. "Die sample remainingon odd input channel l need only disappear during the next eight timeslots in order to insure proper encoding. This greatly reduces the lowfrequency requirements and therefore the bandwidth requirements of thesampling counters resulting in reducing' the cost of the samplingcounters. At the conclusion of the seventh time slot of encoding thesecond sample, all the ipaiiops are again reset. Even input channel 2and its associated circuitry is rendered inoperative and odd channelinput l and its associated circuitry is actuated. r.the encoding processcontinues in the manner above described. Y

FG. 3 illustrates the results achieved by this invention. In line (a) ofFIG. 3 the PAM samples applied to the odd input channel 1 are shown;line (b) of PIG. 3 shows the PAM samples applied to even input channel2. v

The pulses shown in line (c) of FIG. 3 represent the output of errorampliiier 39 when the odd channel input 1 is actuated; the pulses shownin line (d) of HG. 3 represent the output of error vamplifier Ill wheneven channel input 2 is actuated. Since odd input channel 1 is notoperative during the second sample, the signal remaining on the oddinput channel l produces no spurious eiect on the total output of theencoder. Similarly, there is no spurious output produced by the evenchannel input 2 during the iirst and third samples since the evenchannel is rendered inoperative during these samples. AThe total outputof the encoder is shown in line (c) oi FIG. l3 and is the sum of theoutputs shown in lines (c) and (d) of FIG. 3. Y i Y The output appearingat terminal 46 of the blocking oscillator is the inverse of the usualnbinary code. That is to say, if the sample is sufficient in amplitudeto cause current to ow into the error ampliiierno outputrpulse isproduced; if the error amplifier must supply current to the weightingresistors an output pulse is produced. This outputV contains all theinformation contained'in the usual binary code and is usuallytransmitted without the 'necessity of conversion to the usual 'binarycode.

lt is to be understood that the above-described arrangementsarerillustrative of the application of the invention.

skilled in the art without departing from the spirit and scope of theinvention.

What is claimed is:

1. A substantially crosstalk-free pulse code modulation encoding systemfor converting a succession of signal amplitude samples into acorresponding succession of coded sequences of marks and spaces, themarks and spaces of each coded sequence occupying a predetermined numberof consecutive time slots, which comprises a pair of input channelscarrying respectively alternate ones of a succession of signal amplitudesamples, a source of a control pulse which is generated between theoccurrence of each of said coded sequences of marks and spaces, a rstweighted network for weighing only those signal am plitude samplesappearing in one of said input channels, a second weighted network forweighing only those signal amplitude samples appearing in the other ofsaid input channels, logic circuitry common to both of said weightednetworks for controlling the sequential operation of said weightednetworks so that under the control of said common logic circuitry eachof said weighted networks functions as an encoder, a common outputchannel, and a transfer gate responsive to said control pulse which isgenerated between the occurrence of each coded sequence of marks andspaces for connecting said iirst and second weighted networksalternately to said common output channel in synchronism with thesequence of said amplitude samples in said input channels.

2. A substantially crosstalk-free puise code modulation encoding systemwhich comprises a pair of input channels carrying respectively alternateones of a succession ot signal amplitude samples, a iirst sequentiallyoperated encoding network for encoding only those signal amplitudesamples appearing in one of said input channels, a second sequentiallyoperated encoding network for encoding only those signal amplitudesamples appearing in the other of said input channels, a common controlcircuit for controlling the sequential operation of both of saidencoding networks, a common output channel, a transfer gate forconnecting said first and second encoding networks alternately to saidcommon output channel in synchronism with the sequence of signalamplitude samples in said input channels, and means for feeding backencoded samples from said common output channel to said common controlcircuit to control the operation thereof.

3. A substantially crosstalk-free system for converting a succession ofsignal amplitude samples into a corresponding succession of codedsequences of marks and spaces, the marks and spaces of each said codedsequence occupying a predetermined number of consecutive time slots,which comprises a pair of input channels carrying respectively alternateones of said succession of signal amplitude samples, means in each ofsaid input channels for comparing said signal amplitude samples withsuccessively different amplitude standards during successive time slots,means in each of said input channels for generating a mark or a spaceduring each time slot depending upon whether a signal 4amplitude sampleis greater or lesser than the amplitude standard with which it iscompared during that time slot, a common output channel, a transfer gatefor supplying sequences of marks and spaces from said input channel-alternately to said output channel in synchronism with the sequence ofsignal amplitude samples in said input channel, and means for feedingback marks and spaces from said common output channel to determine themagnitudes of said successive diierent amplitude standards in each ofsaid input channels.

References Cited in the file of this patent UNITED STATES PATENTS2,504,354 Roschke Apr. 18, 1950 2,636,081 Feldman Apr. 21, 19532,946,851 Kretzmer July 26, 1960 FOREIGN PATENTS 686,439 Great BritainJan. 2l, 1953 OTHER REFERENCES Meacham et al.: An ExperimentalMultichannel Pulse Code Modulation System of Toll Quality, The BellSystem Technical Journal, January 1948, pp. 1-43 relied on.

Shunaman: Pulse Code Modulation, Radio-Craft, February 1948, pp. 28-30and 47 relied on.

1. A SUBSTANTIALLY CROSSTALK-FREE PULSE CODE MODULATION ENCODING SYSTEMFOR CONVERTING A SUCCESSION OF SIGNAL AMPLITUDE SAMPLES INTO ACORRESPONDING SUCCESSION OF CODED SEQUENCES OF MARKS AND SPACES, THEMARKS AND SPACES OF EACH CODED SEQUENCE OCCUPYING A PREDETERMINED NUMBEROF CONSECUTIVE TIME SLOTS, WHICH COMPRISES A PAIR OF INPUT CHANNELSCARRYING RESPECTIVELY ALTERNATE ONES OF A SUCCESSION OF SIGNAL AMPLITUDESAMPLES, A SOURCE OF A CONTROL PULSE WHICH IS GENERATED BETWEEN THEOCCURENCE OF EACH OF SAID CODED SEQUENCES OF MARKS AND SPACES, A FIRSTWEIGHTED NETWORK FOR WEIGHING ONLY THOSE SIGNAL AMPLITUDE SAMPLESAPPEARING IN ONE OF SAID INPUT CHANNELS, CHANNELS, LOGIC CIRCUITRYCOMMON TO BOTH OF SAID WEIGHTED NETWORKS FOR CONTROLLING THE SEQUENTIALOPERATION OF SAID WEIGHTED NETWORKS SO THAT UNDER THE CONTROL OF SAIDCOMMON LOGIC CIRCUITRY EACH OF SAID WEIGHTED NETWORKS FUNCTIONS AS ANENCODER, A COMMON OUTPUT CHANNEL, AND A TRANSFER GATE RESPONSIVE TO SAIDCONTROL PULSE WHICH IS GENERATED BETWEEN THE OCCURRENCE OF EACH CODEDSEQUENCE OF MARKS AND SPACES FOR CONNECTING SAID FIRST AND SECONDWEIGHTED NETWORKS ALTERNATELY TO SAID COMMON OUTPUT CHANNEL INSYNCHRONISM WITH THE SEQUENCE OF SAID AMPLITUDE SAMPLES IN SAID INPUTCHANNELS.